1. Field of the Invention
The present invention relates to a complementary MOS semiconductor device having a resistor circuit structured on an SOI (silicon on insulator) substrate, in which a low voltage operation, low power consumption, and high driving capability are required, and particularly to a power management semiconductor device such as a voltage detector (hereinafter referred to as VD), a voltage regulator (hereinafter referred to as VR), or a switching regulator (hereinafter referred to as SWR) or an analog semiconductor device such as an operational amplifier or a comparator.
2. Description of the Related Art
Complementary MOS semiconductor devices having a resistor circuit in which a resistor is formed of polycrystalline silicon or the like are widely used. FIG. 18 shows the structure of a conventional semiconductor device provided with a resistor circuit. The semiconductor device is composed of a complementary MOS structure (hereinafter referred to as CMOS) which is comprised of an n-channel MOS transistor (hereinafter referred to as NMOS) a gate electrode of which is comprised of n+ polycrystalline silicon and a p-channel MOS transistor (hereinafter referred to as PMOS) which is formed in an n-well region and a gate electrode of which is also comprised of n+ polycrystalline silicon, and a resistor which is formed on a field insulating film and which is used for a voltage dividing circuit for dividing a voltage or a CR circuit for setting a time constant, which are all formed on a p-type semiconductor substrate (for example, refer to patent document 1)
JP 10-303315 A (page. 1, and FIG. 1)
In the complementary MOS (CMOS) semiconductor device having a resistor circuit, n+ polycrystalline silicon is often used for a gate electrode in view of the ease of manufacture and stability. In this case, an NMOS is a surface channel type based on the relationship of a work function between the gate electrode and the semiconductor substrate while in a PMOS, a threshold voltage is about xe2x88x921 V based on the relationship of a work function between the gate electrode and the semiconductor substrate. Thus, when impurity implantation is conducted in order to reduce the threshold voltage, the PMOS becomes a shallow buried channel type in which a channel is formed in the portion that is beneath the surface of the substrate. The buried channel type has an advantage that mobility is high since a carrier passes through the interior of the substrate. However, in the buried channel type device, when the threshold voltage is lowered, the subthreshold characteristics are severely deteriorated, which leads to an increase in leak current. Therefore, it is more difficult to attain a lower voltage and a shorter channel in the PMOS than in the NMOS.
Further, as a structure that realizes a lower voltage in both the NMOS and the PMOS, there is known the same polarity gate structure in which the polarity of a gate electrode is the same as the polarity of a transistor, as shown in FIGS. 19 or 20. In this structure, n+ polycrystalline silicon is used for the gate electrode of an NMOS transistor and p+ polycrystalline silicon is used for the gate electrode of a PMOS transistor. Thus, both the NMOS transistor and the PMOS transistor are of the surface channel type, which can suppress a leak current, thereby being capable of attaining a lower voltage. However, the number of manufacturing steps is increased because the polarities of the gate electrodes are different from each other, which invites an increase in manufacturing cost and manufacturing time. Further, in an inverter circuit, which is the most basic type of circuit element in general, a connection between the gates of the NMOS and the PMOS through metal is avoided in order to improve surface efficiency. The inverter circuit is laid out with one continuous polycrystalline silicon or a polycide structure that consists of a laminated structure of polycrystalline silicon and high melting point metal silicide from the NMOS to the PMOS in a plane manner. Then, there are problems in terms of costs and characteristics in that, in the case of the polycrystalline silicon single layer shown in FIG. 19, impedance of a pn junction in the polycrystalline silicon is high and thus is unpractical, and in that, in the case of the polycide structure shown in FIG. 20, n-type and p-type impurities diffuse to the gate electrodes having opposite conductivities, respectively, at high speed in the high melting point metal silicide during heat treatment in a step, as a result of which the work function varies, and the threshold voltage is not stable.
Further, in recent years, while reduction in size and reduction in weight has progressed, lower power consumption, higher speed, and increased functionality are required in portable equipment such as portable telephones or PDAs. Along with this, electronic components that constitute the portable equipment need to be reduced in size and operated at a higher speed. However, a power management semiconductor device such as a switching regulator needs to have a withstand voltage of about 10 V, and thus, is difficult to be operated at a higher speed resulting from the attainment of higher definition.
The present invention has been made in view of the above, and therefore an object of the present invention is to provide a complementary MOS semiconductor device which is manufactured at low cost and in a short manufacturing period, enables low voltage operation, and has low power consumption and high driving ability and which can realizes a power management semiconductor device or an analog semiconductor device at high speed operation.
In order to solve the above object, the present invention takes the following means.
(1) There is provided a SOI complementary MOS semiconductor device, which is constituted by an n-type MOS transistor, a p-type MOS transistor, and resistors which are formed on a semiconductor thin film layer in an SOI (silicon on insulator) substrate which is constituted by an insulating film formed on a semiconductor substrate and the semiconductor thin film layer formed on the insulating film, in which: a polarity of a gate electrode of the n-type MOS transistor is p-type; a polarity of a gate electrode of the p-type MOS transistor is p-type; and the resistors are formed of a material different from that for the p-type gate electrode of the n-type MOS transistor and the p-type gate electrode of the p-type MOS transistor.
There is provided a SOI complementary MOS semiconductor device, in which:
(2) the p-type gate electrode of the n-type MOS transistor and the p-type gate electrode of the p-type MOS transistor are formed of first polycrystalline silicon;
(3) the p-type gate electrode of the n-type MOS transistor and the p-type gate electrode of the p-type MOS transistor are formed of a laminate polycide structure that consists of a lamination layer of first polycrystalline silicon and first high melting point metal silicide;
(4) the resistors are formed of second polycrystalline silicon that is different from a material for the p-type gate electrode of the n-type MOS transistor and the p-type gate electrode of the p-type MOS transistor;
(5) the resistors formed of the second polycrystalline silicon include at least a first n-type resistor at a relatively low concentration;
(6) the resistors formed of the second polycrystalline silicon include at least a second n-type resistor at a relatively high concentration;
(7) the resistors formed of the second polycrystalline silicon include at least a first p-type resistor at a relatively low concentration;
(8) the resistors formed of the second polycrystalline silicon include at least a second p-type resistor at a relatively high concentration;
(9) the p-type gate electrode formed of the first polycrystalline silicon has a film thickness of 2000 xc3x85 to 6000 xc3x85;
(10) in the p-type gate electrode formed of the laminate polycide structure that consists of the lamination layer of the first polycrystalline silicon and the first high melting point metal silicide, the first polycrystalline silicon has a thickness of 500 xc3x85 to 2500 xc3x85, and the first high melting point metal silicide has a thickness of 500 xc3x85 to 2500 xc3x85;
(11) the resistors formed of the second polycrystalline silicon each have a thickness of 500 xc3x85 to 2500 xc3x85;
(12) the first n-type resistor at a relatively low concentration which is formed of the second polycrystalline silicon contains phosphorous or arsenic at an impurity concentration of 1xc3x971014 to 9xc3x971018 atoms/cm3, and the sheet resistance value is approximately several kxcexa9/xe2x96xa1 to several tens kxcexa9/xe2x96xa1;
(13) the second n-type resistor at a relatively high concentration which is formed of the second polycrystalline silicon contains phosphorous or arsenic at an impurity concentration of 1xc3x971019 to 5xc3x971021 atoms/cm3, the sheet resistance value is approximately 100 xcexa9/xe2x96xa1 to several hundreds xcexa9/xe2x96xa1, and the temperature coefficient is approximately several hundreds ppm/xc2x0 C. to several thousands ppm/xc2x0 C.;
(14) the first p-type resistor at a relatively low concentration which is formed of the second polycrystalline silicon contains boron or BF2 at an impurity concentration of 1xc3x971014 to 9xc3x971018 atoms/cm3, and the sheet resistance value is approximately several kxcexa9/xe2x96xa1 to several tens kxcexa9/xe2x96xa1;
(15) the second p-type resistor at a relatively high concentration which is formed of the second polycrystalline silicon contains boron or BF2 at an impurity concentration of 1xc3x971019 to 5xc3x971021 atoms/cm3, the sheet resistance value is approximately several hundreds xcexa9/xe2x96xa1 to 1 kxcexa9/xe2x96xa1, and the temperature coefficient is approximately several hundreds ppm/xc2x0 C. to several thousands ppm/xc2x0 C.;
(16) the resistor consists of a thin film metal resistor that is comprised of Nixe2x80x94Cr alloy, chrome silicide, molybdenum silicide, or xcex2-ferrite silicide, and has a thickness of 100 xc3x85 to 300 xc3x85;
(17) the first polycrystalline silicon that forms the p-type gate electrode of the n-type MOS transistor and the p-type gate electrode of the p-type MOS transistor contains boron or BF2 at an impurity concentration of 1xc3x971018 atoms/cm3 or more;
(18) the first high melting point metal silicide is tungsten silicide, molybdenum silicide, titanium silicide, or platinum silicide;
(19) the n-type MOS transistor and the p-type MOS transistor at least include a MOS transistor having a first structure that is a single drain structure in which a source and a drain are each comprised of a diffusion layer at a high impurity concentration which overlaps the p-type gate electrode in a plane manner;
(20) the n-type MOS transistor and the p-type MOS transistor at least include a MOS transistor having a second structure which is constituted by a diffusion layer at a low impurity concentration in which a source and a drain overlap the p-type gate electrode in a plane manner and a diffusion layer at a high impurity concentration in which only a drain does not overlap the p-type gate electrode or both of the source and drain do not overlap the p-type gate electrode;
(21) the n-type MOS transistor and the p-type MOS transistor at least include a MOS transistor having a third structure: which is constituted by a diffusion layer at a low impurity concentration in which a source and a drain overlap the p-type gate electrode in a plane manner and a diffusion layer at a high impurity concentration in which only a drain does not overlap the p-type gate electrode or both of the source and drain do not overlap the p-type gate electrode; and in which an insulating film between the diffusion layer at a high impurity concentration and the p-type gate electrode is thicker than a gate insulating film;
(22) the n-type MOS transistor and the p-type MOS transistor at least include a MOS transistor having a fourth structure which is constituted by a diffusion layer at a high impurity concentration in which a source and a drain overlap the p-type gate electrode in a plane manner and a diffusion layer at a low impurity concentration in which only a drain or both of the source and drain extend more to the channel side than the diffusion layer at a high impurity concentration and overlap the p-type gate electrode in a plane manner;
(23) an impurity concentration of the diffusion layer at a low impurity concentration in each of the second structure MOS transistor, the third structure MOS transistor and the fourth structure MOS transistor is 1xc3x971016 to 1xc3x971018 atoms/cm3, and an impurity concentration of the diffusion layer at a high impurity concentration in each of the first structure MOS transistor, the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor is 1xc3x971019 atoms/cm3 or more;
(24) an impurity of the diffusion layer at a low impurity concentration in each of the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor of the n-type MOS transistor is phosphorous, and an impurity of the diffusion layer at a high impurity concentration in each of the first structure MOS transistor, the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor of the n-type MOS transistor is arsenic or phosphorous;
(25) an impurity of the diffusion layer at a low impurity concentration in each of the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor of the p-type MOS transistor is boron or BF2, and an impurity of the diffusion layer at a high impurity concentration in each of the first structure MOS transistor, the second structure MOS transistor, the third structure MOS transistor, and the fourth structure MOS transistor of the p-type MOS transistor is boron or BF2;
(26) the n-type MOS transistor includes a first n-type MOS transistor having a threshold voltage of buried channel type and enhancement type;
(27) the n-type MOS transistor includes a second n-type MOS transistor having a threshold voltage of buried channel type and depletion type;
(28) the p-type MOS transistor includes a first p-type MOS transistor having a threshold voltage of surface channel type and enhancement type;
(29) the p-type MOS transistor includes a second p-type MOS transistor having a threshold voltage of buried channel type and depletion type;
(30) the semiconductor thin film layer has a thickness of 0.1 xcexcm to 1 xcexcm;
(31) the insulating film formed on the semiconductor substrate has a thickness of 0.1 xcexcm to 1 xcexcm;
(32) the insulating film formed on the semiconductor substrate is formed of an insulating material such as glass, sapphire, or ceramic such as a silicon oxide film or a silicon nitride film;
(33) an element separation structure formed on the semiconductor substrate consists of an insulating film formed by a LOCOS method;
(34) an element separation structure formed on the semiconductor substrate is a trench element separation structure in which the semiconductor thin film layer is etched to the depth that reaches the buried insulating film to form a concave portion;
(35) The interior of the concave portion of the trench element separation structure is filled by a deposited insulating film; or
(36) The interior of the concave portion of the trench element separation structure is filled by third polycrystalline silicon different from the material for the p-type gate electrode and for the resistor comprised of the second polycrystalline silicon.